This invention relates generally to computer memory, and more particularly to providing a system and method for dynamic random access memory (DRAM) device-level repair via address remappings external to the device.
FIG. 1 depicts a contemporary system composed of an integrated processor chip 100, which contains one or more processor elements and an integrated memory controller 110. In the configuration depicted in FIG. 1, multiple independent cascade interconnected memory interface busses 106 are logically aggregated together to operate in unison to support a single independent access request at a higher bandwidth with data and error detection/correction information distributed or “striped” across the parallel busses and associated devices. The memory controller 110 attaches to four narrow/high speed point-to-point memory busses 106, with each bus 106 connecting one of the several unique memory controller interface channels to a cascade interconnect memory subsystem 103 (or memory module, e.g., a DIMM) which includes at least a hub device 104 and one or more memory devices 109. Some systems further enable operations when a subset of the memory busses 106 are populated with memory subsystems 103. In this case, the one or more populated memory busses 108 may operate in unison to support a single access request.
FIG. 2 depicts a memory structure with cascaded memory modules 103 and unidirectional busses 106. One of the functions provided by the hub devices 104 in the memory modules 103 in the cascade structure is a re-drive function to send signals on the unidirectional busses 106 to other memory modules 103 or to the memory controller 110. FIG. 2 includes the memory controller 110 and four memory modules 103, on each of two memory busses 106 (a downstream memory bus with 24 wires and an upstream memory bus with 25 wires), connected to the memory controller 110 in either a direct or cascaded manner. The memory module 103 next to the memory controller 110 is connected to the memory controller 110 in a direct manner. The other memory modules 103 are connected to the memory controller 110 in a cascaded manner. Although not shown in this figure, the memory controller 110 may be integrated in the processor 100 and may connect to more than one memory bus 106 as depicted in FIG. 1.
During normal system operation, DRAM devices may exhibit persistent failures from individual memory cells and/or groups of cells, including entire rows and columns. Some memory subsystems address this problem by moving the data affected by these failures to an alternate storage location once the failure locations have been identified; this alternate location is commonly provided through an additional DRAM device, with the associated cost and power consumption increase. Nevertheless, DRAM devices generally are fabricated with an over allocation of rows and columns. FIG. 3 depicts a block diagram of a DRAM device 300 with non-redundant memory blocks 306 (made up of rows and columns and individual cells), redundant memory blocks 302 (made up of rows and columns and individual cells). These redundant memory blocks can be utilized to replace a limited number of cells which are initially found to be defective during the normal manufacturing process. This replacement is typically performed using permanent fusing. Often, the number of initially defective cells is far fewer than the number of redundant cells. The end result is that frequently unused good redundant memory blocks exist inside of the DRAM devices but are inaccessible in current practice.